Study of Effectiveness of Circuit Level Leakage Power Optimization Techniques in DSM CMOS Cells


Leakage has been the predominant component of power dissipation in Deep sub micrometer CMOS circuits. The leakage current is constituted by many components like Reverse junction leakage current, Drain and gate induced barrier lowering, sub threshold leakage, gate oxide tunneling, channel punch through effect and more importantly the reverse short channel effect. To restrain this leakage power there are many circuit level techniques which can be applied. This paper intends to present the effectiveness of these techniques and proposes the hybrid technique to reduce the leakage power in DSM CMOS inverter circuit. The proposed work is carried out on 180nm technology node.

  • Abstract
  • Key Words
  • 1. Introduction
  • 2. Leakage Power and Its Constituents
  • 3. The Circuit Level Leakage Power Optimization Techniques
  • 4. Conclusions
  • Acknowledgement
  • References

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