4-Bit Pipeline ADC for Monolithic Active Pixel Sensors


Low voltage low power 4-bits 90Ms/s, 40uw, with DNL (+0.19/−0.4)LSB and INL (+0.47/−0.46)LSB is designed using 0.13um UMC CMOS technology operated with 1.2V voltage supply. The converter is composed of three stages the first, second stages produce 1.5bit/stage and last stage produce 2 bit/stage. Using Bottom-Plate Switching and fully digital error correction which corrects errors due to capacitor mismatch, charge injection, and comparator offsets. The calibration is performed without any additional analog circuitry, and the conversion does not need extra clock cycles.

  • Abstract
  • Key Words
  • 1 Introduction
  • 2. Pipeline ADC Architecture
  • 3 Design of a 4Bit Pipeline ADC
  • 4. Results
  • Conclusion
  • References

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