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Mash 2-1 Multi-Bit Sigma-Delta Modulator for WLAN

Excerpt

This paper mainly explores how oversampling and feedback can be employed in high-resolution (Σ-Δ) modulators to extend the signal bandwidth into the range of megahertz, where oversampling ratio is constrained. A 2-1 cascaded multi-bit architecture suitable for broad-band applications is presented, and a linearization technique referred to as partitioned data weighted averaging (DWA) is introduced to suppress in-band digital-to-analog converter (DAC) errors. All blocks implement in the popular MATLAB/SIMULINK environment. The proposed set of blocks also takes into account most of non-ideal factors on sigma-delta modulator. As shown in the experimental results, for a 1 MHz signal bandwidth and −3dBFS input signal, the MASH 2-1 4-bit sigma-delta modulator can achieve 52.5 dB SNDR (signal to noise-and-distortion rate) at a 24Msample/s Nyquist conversion rate with an oversampling ratio of 16.

  • Abstract
  • Key Words
  • 1. Introduction
  • 2. Single Loop Multi-Bit Sigma-Delta Modulator
  • 3. Design of 2-1 Cascaded 4-Bit Sigma-Delta Modulator
  • 4. Non-Idealities for Sigma-Delta ADC
  • 5. Dwa for Multi-Bit DAC
  • 6. Conclusion
  • Acknowledgement
  • References

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