0
Speedup Resilience: A Practical Metric to Explore the Performance Boundary of Multicore Architectures

Excerpt

The continuous improving of semiconductor technology makes the ubiquity of multicore system. In order to understand the potential performance limitation of various multicore systems, we propose a performance metric, speedup resilience, to evaluate the potential possibility performance enhancement of a multicore system. Instead of theoretical metrics provided by vendors, this study evaluates five variant multicore systems by using four benchmarks with different computing characteristics. These benchmarks are parallelize by Pthread and OpenMP paradigms, then compiled by native compilers of the target machine with highest optimizing level. The speedup resilience of these architectures are provided and discussed later. The proposed results also illustrate that branch density and memory contention will largely degrade the performance. Wish this work will be the preliminary step of who want to explore the optimizing space of the software on multicore systems.

  • Abstract
  • Keywords
  • Introduction
  • Overview of Parallel Programming Paradigms
  • Multicore Architectures
  • Experimental Results
  • Comparison of Execution Time of PI Calculation
  • Conclusions
  • Acknowledgment
  • References
Topics: Architecture

Related Content

Customize your page view by dragging and repositioning the boxes below.

Related Journal Articles
Related eBook Content
Topic Collections

Sorry! You do not have access to this content. For assistance or to subscribe, please contact us:

  • TELEPHONE: 1-800-843-2763 (Toll-free in the USA)
  • EMAIL: asmedigitalcollection@asme.org
Sign In