Defect Rate Analysis & Reduction of MPSOC Through Run Time Reconfigurable Computing with Multiple Caches


The blind increase in the CMOS scaling technology has brought us to a stage where it has reached its saturation point. In here, after laying the basis of this work by having a look at the technology trend, a rising problem is addressed that is faced in manufacturing an MPSOC. Than the discussion is switched at reconfigurable computing architecture and it is extended till run-time reconfigurable computing to lead us to the point that how this scheme can reduces the defect rate problem of MPSOC manufactures. Furthermore, the work concludes at proposing a run time reconfiguring technology for MPSOCs as a replacement technology to reduce defect rates and enhance reliability through fault tolerance. The point emphasized than is that why not the leading market vendors switch towards this technology instead of suffering from all the high defect rates in their fabrication. This paper is not only a research review and proposal of new technology but also another step in the efforts for laying basis of reconfigurable computing as a future of computing technologies in context with problem which modern technology is facing today.

  • Abstract
  • 1. Introduction
  • 2. Reconfigurable Computing and Architectures
  • 3. Run Time Reconfiguration
  • 4. Reconfigurable System
  • 5. Defect Rate Reduction
  • 6. Proposed Future Technology for Multi-Core Microprocessor Fabrication
  • 7. Conclusion
  • References

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